Is Lunar Lake proof that Intel is splitting into two different companies?

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The AI ​​war and the race for energy efficiency have pushed Intel engineers to choose the best available technologies by beginning the development of the new Lunar Lake chip, details of which the giant Intel unveiled at the Computex 2024 trade show Among the specifications of this chip, with which Intel hopes not only to obtain supremacy in AI power but also to catch up in terms of energy consumption compared to Apple, one detail is important: the engraving of its chip.

Just like some competitors, Intel built its processor with scraps of chips, and assembled these pieces in its own factories with its own technologies. But, to the amazement of some commentators, the two logic blocks are engraved by the first founder on the planet, the Taiwanese TSMC – the calculation part (compute) in 3 nm (N3B) and the inputs and outputs (I/O) in 6 nm (N6). This while the foundry part of Intel, the IFS (Intel Foundry Service), is in full quest to recover the leadership in engraving through the plan 5 nodes in 4 years (5N4Y, four engraving nodes in 4 years, editor’s note).

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Admission of failure on the part of Intel factories? Nope.

The best nodes to make the best chips

The two main tiles were manufactured by TSMC in order to meet the requirements of the specifications established more than two/three years ago.

The two main tiles were manufactured by TSMC in order to meet the requirements of the specifications.

©Intel

When we started work on Lunar Lake, we selected the best nodes available on the market“, explains Ori Lempel, lead principal engineer in charge of P-Core development at Intel. “We had very tight targets for frequency and energy. And at the time (it takes several years to develop a chip), TSMC's N3B process was the most suitable.

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Intel's goals were to design a very energy-efficient chip. When laying the foundations for manufacturing, only the TSMC N3B node met these specifications. The engineers therefore chose this partner rather than being forced to use Intel factories as was...

Intel's goal was to design a very energy-efficient chip. When laying the foundations for manufacturing, only the TSMC N3B node met these specifications.

© Inte

Same story for Arik Gihon, in charge of the design of the SoC. “The decoupling from factories is real. We have a very strict roadmap and we must stick to it. Of course, we hope to not always depend on TSMC with the arrival of future nodes like the 20A then the 18A. But to make our processors, we now select the best nodes. And this competition is good for innovation and business“, assures the engineer.

In short: engineers in charge of microarchitectures and those dedicated to managing the final construction of SoCs (system on a chip, all-in-one chip) have new design tools for their processors. And they assured us that they had started to migrate from in-house software to that of Cadence and Synopsys, the market standards.

In addition, the very design of hearts has changed philosophy, moving from a myriad of very small blocks (FUBS, for Functional Unit Block) to cells. Larger and more easily interchangeable elements. And above all, meeting standards: “We went from a sea of ​​FUBS, only manageable by our proprietary tools and blocked on a specific node, to a sea of ​​basic cells. Fewer cells at the same time [ce qui réduit la complexité de manipulation] and above all almost independent of the manufacturing method“.

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And thus, more independent of the Intel factories for which the company's tools were until now optimized. If this evolution was specifically implemented from the start of the development of the high-power Lion Cove cores (the P-Cores), Intel engineers assured us that this was a general trend. However, the choice of TSMC is not a renunciation for Intel in the race for engraving finesse. It simply shows that the company embraces competition to have it both ways.

Intel in a double race

Pat Gelsinger, during the question and answer session given to the press on June 4, 2024 at Computex in Taipei.

Pat Gelsinger, during a question and answer session with the press, June 4, 2024 at Computex in Taipei.

© Adrian Branco for Les Numériques

During a question and answer session by Pat Gelsinger with the press at Computex, to which the editorial staff Digital participated, the boss of Intel assured that “if the Lunar Lake teams chose TSMC at the time, next year Panther Lake [la prochaine génération de puces mobiles, ndlr] will mainly be designed using our Intel 18A process. And our first wafer validating the process (18A) left our factories last week!“, welcomed the boss of Intel. Intel, whose foundry division (IFS, Intel Foundry Service) is incidentally the first (and only) in the world to have acquired the EUV High-NA machines, which should make it possible to reach 1 nm.

Pat Gelsinger, during the keynote on June 4, 2024 at Computex in Taipei.

Pat Gelsinger, during the keynote on June 4, 2024 at Computex in Taipei.

© Adrian Branco for Les Numériques

Pat Gelsinger now has two hats for two companies which bear the same name, but have very different and now very clear missions: an Intel responsible for designing the best chips in the world, and which now seems to have complete freedom to seek out the most efficient processes. more suitable to achieve its ends. And an industrial Intel, a chip manufacturer, which intends to regain its technological leadership and produce as many chips as possible. Even if it means serving your enemies of yesterday and today. “We want to become the second largest foundry in the world by the end of the decade and manufacture for everyone“, insisted Pat Gelsinger.

A duality which could, ultimately, lead to a split in Intel's activities? The future will tell.

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