Intel engraves in 3 nm and returns to the miniaturization race

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Intel is backthe CEO of the firm, Pat Gelsinger, professes to anyone who will listen. If the company remains battered on the stock market and continues with huge projects (construction of factories, etc.), Intel can celebrate a victory: that of the implementation volume production of its Intel 3 engraving nodea competitor of TSMC 3, which we will call 3 nm for convenience. This is the third node of its strategy “5 nodes in 4 years“(5N4Y) that the company manages to finalize.

Intel engraves in 3 nm and returns to the miniaturization race

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After announcing that the node was technologically ready at the end of last year, the current announcement is even more important: this time it is about mass production, the nerve of war in the world of semiconductors. Indeed, it has been a long time since IBM demonstrated the production of components in 2 nm. But between a lab production to produce a small wafer and the establishment of production lines capable of producing millions of chips at a moderate cost, there is a world of difference.

The latest FinFET node for Intel

Intel engraves in 3 nm and returns to the miniaturization race

Intel says this is its latest node to use a finned transistor design, or FinFET in the jargon (end field-effect transistor). After its design in the laboratories of the Hitachi Central Research Laboratory in 1989 in Japan and years of testing by the big names in engraving at the time, it was Intel that mass-marketed the first chips using this structure for its Core Ivy Bridge processors from 2011.

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Intel engraves in 3 nm and returns to the miniaturization race

Instead of the planar structure (planar) of previous production models of the MOSFET era, FinFET transistors add a fin that makes the structure three-dimensional. The benefit is better circuit isolation leading to less heat dissipation, lower power consumption and easier chip growth.

Intel 3 will therefore ringfor Intel, the end of an era. An era that began under the domination of the American player and ended with that of the Taiwanese TSMC. The Intel node 3 is therefore not yet the one that will propel Intel into the era of GAAFET (gate all around field effect transistors). This more complex and more advanced structure will be adopted from Intel 20A.

Intel 3: one node, several variants

Intel engraves in 3 nm and returns to the miniaturization race

Just like TSMC, which has variants in its nodes depending on whether the targets are low-power or high-performance chips (e.g. N3E or N3P), Intel now communicates on several nodes – normal, the firm is now a foundry serving other customers.

Intel engraves in 3 nm and returns to the miniaturization race

  • Intel 3: The Basic Node for Monolithic Chip Design
  • Intel 3-T: a node suitable for designing disaggregated processors (we stack bits of chips). It is in fact optimized to support interconnections through silicon (TSV, Through Silicon Via).
  • Intel 3-E: a node that provides a large number of input/output (I/O in the jargon) tools to add external memory interfaces, analog components and the like.
  • Intel 3-PT: A node that Intel says combines all of the above capabilities and should be preferred by the industry for its additional performance gains, ease of use for chip designers, finer TSV links, etc.

The reason why Lunar Lake is engraved by TSMC

The two tiles of Lunar Lake are etched by TSMC. The computational tile (called

Both Lunar Lake tiles are etched by TSMC. The compute tile is etched in N3B, the competitor of Intel's node 3.

© Adrian BRANCO for Les Numériques

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If you follow the news surrounding processor launches, you've probably noticed that Intel's next mainstream mobile chip, Lunar Lake, will be partly manufactured on a 3nm node… but by TSMC.

Sunday commentators will therefore not fail to point out the quality of Intel's production. A production for which, at present, there is no quality analysis (transistor density, heating, etc.) or performance – nothing to form an opinion on at the technical or economic level. There is a perfectly rational and logical explanation for the fact that the Lunar Lake logic brick is engraved in TSMC N3, and not with this Intel node. This explanation has nothing technical, but relates to the schedule and methodology of chip development.

As we told you about it in this articleIntel CEO Pat Gelsinger is separating Intel's operations. Instead of being confined to Intel's factories, the engineers who designed Lunar Lake have been given free rein. According to Arik Gihon, an Intel engineer in charge of Lunar Lake's design whom we were able to interview during Computex in Taipei, his “mission was to design the chip with the best performance/watt ratio. And we had complete freedom to choose the processes suited to the design of such a chip.“.

However, it takes between two and five years to design and market such a complex chip. While Intel has just announced the launch of mass production of its Intel Node 3 in June 2024, TSMC had started launching factories in December 2022. You don't need to be a rocket scientist to understand that at the time of the conceptualization of the Lunar Lake bricks, the only node guaranteed to be on time was that of TSMC, which is therefore almost two years ahead of Intel.

Intel engraves in 3 nm and returns to the miniaturization race

A lead that is shrinking every quarter. And which should shrink further by the end of the current year, since the Arrow Lake desktop PC chips should be engraved, at least in part, with the new Intel 20A node — which could be described as 2 nm, even if that is not entirely accurate.

If Intel can ramp up this node — what yields? — and to combine quality and quantity on the next node, Intel 18A planned for mid-2025, the American will have succeeded in its technological bet: launching five nodes in four years (5N4Y). It will then be up to Intel to transform the test by finding customers for its factories. And to never again be left behind, as TSMC has done in recent years. Easier said than done.

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